Spatial and temporal stability of vision chips including parasitic inductances and capacitances

There are two dynamics issues in vision chips: (i) The temporal! dynamics issue due to the parasitic capacit,ors in a CMOS chip, and (ii) the spatial dynamics issue due t,o the regular array of processing elements in a chip. These issues are discussed in [l: 2, 31 for the resistor network with only associated parasitic capacitances. However, in this paper we consider also parasitic inductances as well as parasitic capacitances for a more precise network dynamics model. We show that, in some cases the temporal stability condition for the network with p‘ar<a.sitic indllctances and capacitances is equivalent to that. for the net.work with only pasasitic capacitances, but in general they are not equivalent. We also show that the spatial stability conditions are equivalent. in both c‘ases. Key Wo77l.s : Network Stability, Vision Chip, Neuro Chip, Neural Network